Consumer electronics requirements demand more integrated circuits in an integrated circuit package while paradoxically providing less physical space in the system for the increased integrated circuits content. Continuous cost reduction is another requirement. Some technologies primarily focus on integrating more functions into each integrated circuit. Other technologies focus on stacking these integrated circuits into a single package. While these approaches provide more functions within an integrated circuit, they do not fully address the requirements for lower height, smaller space, and cost reduction.
One proven way to reduce cost is to use mature package technologies with existing manufacturing methods and equipments, or in some cases eliminate some of the existing steps and equipments. Paradoxically, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions. Still the demand continues for lower cost, smaller size, and more functionality.
Stacking more integrated circuits into a package is one way to squeeze more integrated circuit content into smaller real estate. Thinning the wafers and integrated circuits provide lower height integrated circuit stacks and packages. As the thinning process evolves to more aggressive “thinness” of the wafers and the integrated circuits, the thinned integrated circuits are more prone to damage throughout the silicon manufacturing and packaging processes.
Existing stacked packages, in case of same size integrated circuit die application, requires separate spacer attachment between upper and lower integrated circuit die to lift up the upper integrated circuit die for enabling wire bonding and preventing wires from touching the edge of the lower integrated circuit die. Typically, a spacer is silicon die or film and prepared by additional semiconductor assembly processes. The silicon spacer manufacturing and packaging processes requires the spacer wafer thinning, the spacer wafer mount and sawing, and the spacer attach and cure. The film spacer calls for the cut and place process.
The silicon spacer handling throughout the manufacture and package assembly processes constrains the spacer patterns and size. Similarly, film or paste spacers also constrain the spacer patterns and size. Both processes do not keep pace with the shrinking geometries of integrated circuits without changes/capital investments to the manufacture processes and equipments, do not optimally support the continued reduction of the integrated circuit thickness, and do not optimally provide lower package height.
Thus, a need still remains for an integrated circuit packaging system low cost manufacturing as well as reduce the integrated circuit package height. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.